1. Field of the Invention
The present invention relates to an information processing system and a logic LSI to which a master/checker method is applied, with the objective of improving the fault detection efficiency.
2. Description of Related Art
An information processing apparatus to which a master/checker method is applied, with the objective of improving the fault detection efficiency, already has been presented. For example, an information processing apparatus having the above-mentioned feature is disclosed in "Fault Tolerance Achieved in VLSI", by R. Emmerson et al., IEEE Micro., December 1984, pp 34-43.
In the above-mentioned apparatus, data output from a master unit is input to a checker unit via a data bus. The output data of the master unit input to the checker unit is compared with corresponding output data of the checker unit by a comparator provided in the checker unit. If a result of the comparison indicates a disagreement between both data, the comparator outputs a fault detecting signal, and the operation of the information processing apparatus is stopped.
On the other hand, due to recent rapid innovation in LSI processing techniques, a processor including many peripheral circuits, such as cache memory, has been developed. Therefore, it has been considered not sufficient for fault detection in an apparatus containing a plurality of processors, such as mentioned above, to be carried out merely by comparing a pair of data transmitted to a data bus.
As a method of improving the fault detection efficiency, it also has been proposed to execute a comparison between data output from one of the peripheral circuits integrated in a processor provided in a master unit and data output from a corresponding one of the peripheral circuits integrated in a processor provided with a checker, in addition to the comparison between data output on the data bus. However, if the fault detection is carried out for output data of all integrated circuits in a master unit and a checker, a new problem is caused, that is, a comparator for comparing data processed in the integrated circuits and the wiring among the integrated circuits and the comparators need a large area, respectively.
As a method of resolving the above-mentioned problem, "A fault detection processing method" is disclosed in JP-A-129426/1985 by Hujiwara et al.. In this method, the fault detection is realized by executing a comparison between a result of an exclusive OR calculation for data output from the integrated circuits of a processor in a master unit and a result of an exclusive OR calculation for data output from the integrated circuits of a processor in a checker. Although this method avoids the need to increase the area needed for a comparator and the wiring, faults of 2 bits can not be detected. Therefore, by this method, a sufficient fault detection efficiency can not be attained.